This invention relates to programmable integrated logic circuits. In particular, the invention relates to an improved architecture which implements redundancy capabilities in programmable logic devices.
Programmable logic devices (PLDs), sometimes referred to as PALs, PLAs, FPLAs, PLDs, FPLDs, EEPLDs, LCAs, and FPGAs, are well known. Such devices often comprise a plurality of logic blocks and programmable switch boxes arranged in an array format. Each logic block is configurable to perform user-specified logic operations. Configuration data, which control the logic block functions, are stored in volatile or nonvolatile memory and are loaded at power-up or on command.
It is known in the art that many schemes exist to provide the necessary connections among the logic blocks in a programmable logic device. One scheme involves the use of direct programmable interconnections between adjacent blocks. Special inputs and outputs of adjacent logic blocks can be directly connected via programmable interconnection points. These programmable interconnection points are implemented by programmable switches, such as pass transistors. This scheme is described in detail in the 1992 edition of The Programmable Gate Array Data Book by Xilinx, Inc. of San Jose, Calif.
Another scheme described therein employs general purpose interconnect channels, each of which comprises a plurality of vertical and horizontal metal segments. These general purpose interconnect channels are joined by programmable switching boxes. Circuits within these switching boxes permit programmed interconnections among horizontal and vertical segments, forming an interconnect network for the inputs and outputs of the logic blocks. Signals that must travel long distances are routed via long lines which bypass the programmable switching boxes.
It has long been recognized that logic device yield and reliability are inversely correlated with increased complexity. A defective row or column of logic blocks can render the entire array of logic blocks useless even though the remainder of the array is free of defects. Thus, there is desired an architecture which permits defective rows and/or columns of logic blocks to be bypassed and replaced by redundant rows and/or columns of defect-free logic blocks.